Hi
I do a lot VHDL at work.
What I use mostly are the following Tools+ entries:
##Tools Plus Plugin (v0.6) Command Export##
COMMAND#####################################
name:Compile VHDL file VHDL93 (ModelSim)
command line:C:\Modeltech\win32xoem\vcom -93 -explicit $file
workdir:c:\msimwork
wildcards:*.vhd;*.vhdl
menu string:Simulation/Compile file VHDL93 (ModelSim)
menu priority:100
context menu string:Simulation/Compile file VHDL93 (ModelSim)
context menu priority:100
envvarset:
mode (W,C,):W
COMMAND#####################################
name:Sim (ModelSim)
command line:C:\Modeltech\win32xoem\vsim $fname
workdir:c:\msimwork
wildcards:*.vhd;*.vhdl
menu string:Simulation/Simulate entity (ModelSim)
menu priority:100
context menu string:Simulation/Simulate entity (ModelSim)
context menu priority:100
envvarset:
mode (W,C,):
The drawback, the name of the entity to simulate (the testbench) must match the filename.
The other possibility: GHDL is able to generate makefiles which are easy to use from within codeblocks.
regards danselmi