Hi
Thanks for your patience!
I'd like to do auto indent/unindent for another language (VHDL and
Verilog in addition to c/c++, which is implemented in the core).
indent:
- check if the user entered a '\n' (OnCharAdded)
- check the last non comment word/character
- if the last word is a "begin" (example for Verilog) indent the new line
unindent:
- If the added character was not a '\n'
- check if the current line contains only "end" and spaces
- search the corresponding "begin"
- indent the current line to the same value as the line containing the "begin"
This is near the same mechanism as for C/C++, only the '{' is replaced with "begin"
and the '}' is replaced with "end". For VHDL it is a bit more complicated because we
have to check for more different words/characters but basically it remains
the same mechanism.
As you could see in my first post, I have implemented these things (and the
mechanism which replaces ,, .. ;; with <= => := if they get typed fast enough) in the core.
Now i'd like to share this work (and do some more if needed) with other people.
Because VHDL and Verilog are not that widely used i think it is not realistic to get
these changes in the core.
If I have to implement these features in a plugin, I am not sure which event to
register to cbEVT_EDITOR_MODIFIED? And will this be fast enough?
Daniel